Index

	1T Dynamic RAM (DRAM) Cell [slide]
	1T DRAM Writes and Reads [slide]
	2's Complement Multiplication [slide]
	2's Complement Multiplier [slide]
Why Isn’t This a	20-minute Lecture? [slide]
	32-bit Carry Select Adder [slide]
Extending K-maps to	4-variable Tables [slide]
	5-Stage Pipelined Processors [slide]
Improving	5-Stage Pipeline Performance [slide]
Improving	5-Stage Pipeline Performance [slide]
	5-Stage Pipelined Datapath [slide]
	5-stage Beta: Final Version [slide]
	6.004: The Big Lesson [slide]
	8-bit CLA (generate G & P) [slide]
	8-bit CLA (carry generation) [slide]
	8-bit CLA (complete) [slide]
Information Processing	= Computation [slide]
	ALU Instructions [slide]
	ALU Op Datapath I [slide]
	ALU Op Datapath II [slide]
	ALU Operations (with constant) I [slide]
	ALU Operations (with constant) II [slide]
Beta	ALU Instructions [slide]
Beta	ALU Instructions with Constant [slide]
Can We Solve Factorial with	ALU Instructions? [slide]
	ANDs and ORs with > 2 Inputs [slide]
The Digital	Abstraction [slide]
	Abstraction du jour: Finite State Machines [slide]
Procedures: A Software	Abstraction [slide]
The Power of Engineering	Abstractions [slide]
Cache	Access [slide]
	Accessing User Locations [slide]
Cache Coherence in	Action [slide]
	Activation Records [slide]
Stack Frames as	Activation Records [slide]
MESI	Activity Diagram [slide]
Handler for	Actual Illops [slide]
	Acyclic Combinational Circuits [slide]
And	Add A Little Parallelism... [slide]
Improving Speed:	Adder Example [slide]
32-bit Carry Select	Adder [slide]
Carry Select	Adders [slide]
Carry Look-ahead	Adders (CLA) [slide]
	Adding New SVCs [slide]
MMU	Address Translation [slide]
MMU	Address Translation [slide]
Basic Cache	Algorithm [slide]
Huffman’s	Algorithm [slide]
Coded	Algorithms: Key to CS [slide]
Semaphores for Resource	Allocation [slide]
	Alternatives to Sequential Consistency? [slide]
Control Structure	Alternatives [slide]
From Atoms to	Amazon [slide]
	Amdahl’s Law [slide]
	Amdahl’s Law and Parallelism [slide]
Frontend Stages: Lexical	Analysis [slide]
Frontend Stages: Syntactic	Analysis [slide]
Frontend Stages: Semantic	Analysis [slide]
Performance/Cost	Analysis [slide]
	Anatomy of a Modern Compiler [slide]
	Anatomy of a von Neumann Computer [slide]
Beta: Our “Final	Answer” [slide]
	Ant Schematic [slide]
Here’s a Design	Approach [slide]
Karnuagh Maps: A Geometric	Approach [slide]
	Approach: Incremental Featurism [slide]
Instruction Set	Architecture (ISA) [slide]
Reduce	Area With Sequential Logic [slide]
	Argument Order & BP Usage [slide]
Page Map	Arithmetic [slide]
Example: Page Map	Arithmetic [slide]
How Does It Get	Assembled? [slide]
	Assembly Language [slide]
	Assembly of Instructions [slide]
Example	Assembly [slide]
Summary:	Assembly Language [slide]
	Associativity Tradeoffs [slide]
	Associativity Implies Choices [slide]
Interrupt-based	Asynch I/O [slide]
	Asynchronous I/O Handling [slide]
	Asynchronous Interrupts [slide]
Producer/Consumer	Atomicity Problems [slide]
From	Atoms to Amazon [slide]
ReadKey SVC:	Attempt #1 [slide]
ReadKey SVC:	Attempt #2 [slide]
ReadKey SVC:	Attempt #3 [slide]
ReadKey SVC:	Attempt #4 [slide]
	BEQ/BNE Instructions I [slide]
	BEQ/BNE Instructions II [slide]
Argument Order &	BP Usage [slide]
Okay,	Back to Circuits... [slide]
	Back to Our Bottleneck... [slide]
Interface Standard:	Backplane Bus [slide]
The HW/SW	Balance [slide]
	Basic Cache Algorithm [slide]
Unsolvable? That Can’t	Be True... [slide]
We’ve	Been Designing a MUX [slide]
	Best of Both Worlds: Overlapped Operation [slide]
	Beta ISA Summary [slide]
UASM Macros for	Beta Instructions [slide]
Reminder:	Beta ISA [slide]
	Beta Inside! [slide]
	Beta ISA: Storage [slide]
	Beta ISA: Instructions [slide]
	Beta ALU Instructions [slide]
	Beta ALU Instructions with Constant [slide]
	Beta Load and Store Instructions [slide]
	Beta Branch Instructions [slide]
	Beta JMP Instruction [slide]
	Beta ISA Summary [slide]
Reminder: Single-Cycle	Beta [slide]
Single-Cycle	Beta Performance [slide]
Simplified Unpipelined	Beta Datapath [slide]
	Beta Interrupt Handling [slide]
	Beta: Our “Final Answer” [slide]
5-stage	Beta: Final Version [slide]
Can We Do	Better? [slide]
	Beyond Inverters [slide]
6.004: The	Big Lesson [slide]
Encodings as	Binary Trees [slide]
	Binary Multiplication [slide]
Hamming Distance and	Bit Errors [slide]
Write-back with “Dirty”	Bits [slide]
	Block Size [slide]
	Block Size Trandeoffs [slide]
Sum-of-products Building	Blocks [slide]
More Building	Blocks [slide]
Universal Building	Blocks [slide]
Mr.	Blue Visits the ISS [slide]
Mr.	Blue Visits the ISS (cont&rsquo'd.) [slide]
	Bonk! [slide]
	Boolean Minimization [slide]
Best of	Both Worlds: Overlapped Operation [slide]
Back to Our	Bottleneck... [slide]
Example:	Bounded Buffer Problem [slide]
	Bounded Buffer Problem with Semaphores [slide]
	Bounded Buffer Problem with More Semaphores [slide]
	Bounded Buffer Problem with Even More Semaphores [slide]
The	Bounded-tie Synchronizer [slide]
Thinking Outside the	Box [slide]
Meanwhile, Outside the	Box... [slide]
Beta	Branch Instructions [slide]
	Branch Prediction [slide]
	Branch Delay Slots I [slide]
	Branch Delay Slots II [slide]
ISA Issues: Simple vs. Complex	Branches [slide]
Example: Bounded	Buffer Problem [slide]
Bounded	Buffer Problem with Semaphores [slide]
Bounded	Buffer Problem with More Semaphores [slide]
Bounded	Buffer Problem with Even More Semaphores [slide]
Translation Look-aside	Buffer (TLB) [slide]
FIFO	Buffering [slide]
Let’s	Build a System! [slide]
Let's	Build a RoboAnt [slide]
Something We Can't	Build (Yet) [slide]
Digital State: What We'd Like to	Build [slide]
Sum-of-products	Building Blocks [slide]
More	Building Blocks [slide]
Universal	Building Blocks [slide]
	Building the Transition Table [slide]
	Building a Virtual Machine (VM) [slide]
Interface Standard: Backplane	Bus [slide]
A Parallel	Bus Transaction [slide]
	Bus Lines as Transmission Lines [slide]
Improving on the	Bus [slide]
	Buses, Interconnect, So...? [slide]
	But, What If... [slide]
	Bypass Logic [slide]
Fully	Bypassed Pipeline [slide]
Carry Look-ahead Adders	(CLA) [slide]
8-bit	CLA (generate G & P) [slide]
8-bit	CLA (carry generation) [slide]
8-bit	CLA (complete) [slide]
	CMOS Recipe [slide]
	CMOS Inverter VTC [slide]
	CMOS Comoplements [slide]
General	CMOS Gate Recipe [slide]
	CMOS Gates Are Naturally Inverting [slide]
	CMOS Timing Specifications [slide]
	CMOS Loves Inverting Logic [slide]
	CMOS Sum-of-products Implementation [slide]
	CMOS Static Power Dissipation [slide]
	CMOS Dynamic Power Dissipation I [slide]
	CMOS Dynamic Power Dissipation II [slide]
	CPU Design Tradeoffs [slide]
Processes: Multiplexing the	CPU [slide]
Coded Algorithms: Key to	CS [slide]
Virtual Memory: the	CS View [slide]
	Cache Access [slide]
	Cache Metrics [slide]
Basic	Cache Algorithm [slide]
Direct-Mapped	Cache Problem: Conflict Misses [slide]
Fully-Associative	Cache [slide]
N-way Set-Associative	Cache I [slide]
N-way Set-Associative	Cache II [slide]
Summary:	Cache Tradeoffs [slide]
Fix: “Snoopy”	Cache Coherence Protocol [slide]
Example: MESI	Cache Coherence Protocol [slide]
The	Cache Has Two Customers! [slide]
	Cache Coherence in Action [slide]
	Caches [slide]
Direct-Mapped	Caches [slide]
Example: Direct-Mapped	Caches [slide]
Multicore	Caches [slide]
Reminder: Hardware	Caches [slide]
Using	Caches with Virtual Memory [slide]
Semaphores as a Supervisor	Call [slide]
Procedure	Calling Convention [slide]
OS Organization: Supervisor	Calls [slide]
	Can We Do Better? [slide]
	Can We Solve Factorial with ALU Instructions? [slide]
	Can We Solve Factorial Now? [slide]
Compilers	Can Help [slide]
When	Can Exceptions Happen? [slide]
How	Can We Reduce Power? [slide]
Unsolvable? That	Can’t Be True... [slide]
Something We	Can't Build (Yet) [slide]
Memory: Using	Capacitors [slide]
Truth Tables with Don’t	Cares [slide]
	Carry Select Adders [slide]
32-bit	Carry Select Adder [slide]
Wanted: Faster	Carry Logic! [slide]
	Carry Look-ahead Adders (CLA) [slide]
	Carry-save Pipelined Multiplier [slide]
The	Case for a Non-minimal SOP [slide]
SRAM	Cell [slide]
1T Dynamic RAM (DRAM)	Cell [slide]
Voltage Transfer	Characteristic [slide]
Parity	Check [slide]
Associativity Implies	Choices [slide]
Pipelined	Cicuits [slide]
A Simple Sequential	Circuit [slide]
	Circuit Interleaving I [slide]
	Circuit Interleaving II [slide]
	Circuit Interleaving III [slide]
Sequential	Circuit Timing [slide]
Acyclic Combinational	Circuits [slide]
Single-clock Synchronous	Circuits [slide]
Forget	Circuits... Let’s solve a Real Problem [slide]
Okay, Back to	Circuits... [slide]
The World Doesn’t Run on Our	Clock! [slide]
	Code Generation [slide]
Vector	Code Example [slide]
	Coded Algorithms: Key to CS [slide]
Interrupt Handler	Coding [slide]
Fix: “Snoopy” Cache	Coherence Protocol [slide]
Example: MESI Cache	Coherence Protocol [slide]
Cache	Coherence in Action [slide]
Is This a	Combination Device? [slide]
	Combinational Device Wish List [slide]
The	Combinational Contract [slide]
Acyclic	Combinational Circuits [slide]
	Combinational Devices [slide]
A	Combinational Digital System [slide]
	Combinational Multiplier [slide]
	Combine Techniques [slide]
FETs	Come in Two Flavors [slide]
Where Does Noise	Come From? [slide]
	Common IR: Control Flow Graph [slide]
	Communication Topologies [slide]
	Communication Technologies: Latency [slide]
Interprocess	Communication [slide]
Synchronous	Communication [slide]
	Communicationg with the OS [slide]
Serial, Point-to-point	Communications [slide]
	Communications in Today's Computers [slide]
	Communications Futures [slide]
CMOS	Comoplements [slide]
	Compilation [slide]
Interpretation vs.	Compilation [slide]
A Simple	Compilation Strategy [slide]
Anatomy of a Modern	Compiler [slide]
	Compilers [slide]
	Compilers Can Help [slide]
	Compiling Expressions [slide]
Two’s	Complement Encoding [slide]
More Two’s	Complement [slide]
2's	Complement Multiplication [slide]
2's	Complement Multiplier [slide]
ISA Issues: Simple vs.	Complex Branches [slide]
Pipelined	Components [slide]
Information Processing =	Computation [slide]
Models of	Computation [slide]
Other Models of	Computation [slide]
Other Models of	Computation [slide]
	Computer System Technologies [slide]
The Eniac	Computer [slide]
Key Idea: Stored-program	Computer [slide]
Anatomy of a von Neumann	Computer [slide]
Communications in Today's	Computers [slide]
compile_statement:	Conditional [slide]
Direct-Mapped Cache Problem:	Conflict Misses [slide]
Real-world	Consequences [slide]
Sequential	Consistency [slide]
Alternatives to Sequential	Consistency? [slide]
Should We Support	Constant Operands? [slide]
Beta ALU Instructions with	Constant [slide]
Space & Time	Constraints [slide]
	Contamination Delay [slide]
Example: Information	Content [slide]
Probability and Information	Content [slide]
Rapid	Context Switching [slide]
	Contexts [slide]
	Contexts [slide]
	Contexts: A Sneak Preview [slide]
The Combinational	Contract [slide]
Procedure Linkage: The	Contract [slide]
	Control Logic [slide]
Common IR:	Control Flow Graph [slide]
	Control Flow Graph for GCD [slide]
	Control FSM for Factorial [slide]
	Control FSM Hardware [slide]
A	Control FSM for Factorial [slide]
New Problem → New	Control FSM [slide]
Pipelined	Control [slide]
	Control Hazards I [slide]
	Control Hazards II [slide]
Resolving	Control Hazards [slide]
Resolving	Control Hazards With Stalls [slide]
Stall Logic For	Control Hazards [slide]
Speculation Logic For	Control Hazards [slide]
	Control Structure Alternatives [slide]
	Control Structure Taxonomy [slide]
Flakey	Control Systems [slide]
Flow	Control Problems [slide]
Procedure Calling	Convention [slide]
Storage	Conventions [slide]
Pipeline	Conventions [slide]
Information	Conveyed by Data [slide]
Dealing With Outside	Corners [slide]
Error	Correction [slide]
The Cache Has Two	Customers! [slide]
Example:	Cycle 1 [slide]
Example:	Cycle 2 [slide]
Example:	Cycle 3 [slide]
Example:	Cycle 4 [slide]
Example:	Cycle 5 [slide]
New Device:	D Latch [slide]
Edge-triggered	D Register [slide]
	D-Register Waveforms [slide]
	D-Register Timing [slide]
1T Dynamic RAM	(DRAM) Cell [slide]
1T	DRAM Writes and Reads [slide]
Summary:	DRAM [slide]
Synchronization: The	Dark Side [slide]
Raw	Data [slide]
Information Conveyed by	Data [slide]
	Data Hazards [slide]
Resolving	Data Hazards I [slide]
Resolving	Data Hazards II [slide]
Summary: Pipelining with	Data Hazards [slide]
	Data-Dependent Vector Operations [slide]
	Data-Level Parallelism [slide]
ALU Op	Datapath I [slide]
ALU Op	Datapath II [slide]
	Datapath for Factorial [slide]
A Simple Programmable	Datapath [slide]
Simplified Unpipelined Beta	Datapath [slide]
5-Stage Pipelined	Datapath [slide]
	Deadlock! [slide]
Dealing With	Deadlocks [slide]
	Dealing With Noise [slide]
	Dealing With Outside Corners [slide]
	Dealing With Deadlocks [slide]
Summary of	Dedicated Registers [slide]
VTC	Deductions [slide]
Propagation	Delay [slide]
Contamination	Delay [slide]
Solution:	Delay Increases Reliability [slide]
Branch	Delay Slots I [slide]
Branch	Delay Slots II [slide]
Gates, Wires, &	Delays [slide]
	Demand Paging [slide]
Limits to Pipeline	Depth [slide]
CPU	Design Tradeoffs [slide]
Here’s a	Design Approach [slide]
ISA	Design [slide]
Optimizing Your	Design [slide]
Simple Page Map	Design [slide]
We’ve Been	Designing a MUX [slide]
Implementation	Details [slide]
Stack Frame	Details [slide]
	Detecting Multi-bit Errors [slide]
Error	Detection [slide]
Single-bit Error	Detection [slide]
Stack	Detective [slide]
Combinational	Device Wish List [slide]
New	Device: D Latch [slide]
Is This a Combination	Device? [slide]
Combinational	Devices [slide]
OS Organization: I/O	Devices [slide]
Scheduling of Multiple	Devices [slide]
State Transition	Diagram [slide]
State Transition	Diagram as a Truth Table [slide]
MESI Activity	Diagram [slide]
What’s My Transition	Diagram? [slide]
Valid State	Diagrams [slide]
Pipeline	Diagrams [slide]
Pipeline	Diagrams [slide]
Why	Did Our System Fail? [slide]
The	Digital Abstraction [slide]
A Combinational	Digital System [slide]
	Digital State: What We'd Like to Build [slide]
Using Voltages	Digitally [slide]
Semaphores	(Dijkstra) [slide]
	Dining Philosophers [slide]
	Direct-Mapped Caches [slide]
Example:	Direct-Mapped Caches [slide]
	Direct-Mapped Cache Problem: Conflict Misses [slide]
... With a Little	Discipline [slide]
	Discrete Time, Discrete State [slide]
Discrete Time,	Discrete State [slide]
Model:	Discrete Time [slide]
Non-Volatile Storage: Hard	Disk [slide]
CMOS Static Power	Dissipation [slide]
CMOS Dynamic Power	Dissipation I [slide]
CMOS Dynamic Power	Dissipation II [slide]
Hamming	Distance [slide]
Hamming	Distance and Bit Errors [slide]
Can We	Do Better? [slide]
How	Do 6.004 Students Do Laundry? [slide]
How Do 6.004 Students	Do Laundry? [slide]
How	Does It Get Assembled? [slide]
Where	Does Noise Come From? [slide]
The World	Doesn’t Run on Our Clock! [slide]
	Doing N Loads of Laundry [slide]
	Doing N Loads... The 6.004 Way [slide]
Truth Tables with	Don’t Cares [slide]
Write	Down Equations [slide]
FSMs All the Way	Down? [slide]
1T	Dynamic RAM (DRAM) Cell [slide]
CMOS	Dynamic Power Dissipation I [slide]
CMOS	Dynamic Power Dissipation II [slide]
One VM For	Each Process [slide]
	Edge-triggered D Register [slide]
N-Channel MOSFET:	Electrical View [slide]
	Electrical Model for Real Wires [slide]
	Electricity to the Rescue [slide]
Settable Memory	Element [slide]
	Emulated Instruction: swapreg(Ra,Rc) [slide]
Using Voltages to	Encode a Picture [slide]
	Encoding Information [slide]
	Encoding Postive Integers [slide]
	Encoding Signed Integers [slide]
Two’s Complement	Encoding [slide]
Example: Variable-length	Encoding [slide]
	Encodings [slide]
	Encodings as Binary Trees [slide]
Fixed-length	Encodings [slide]
Variable-length	Encodings [slide]
The	End! [slide]
The Power of	Engineering Abstractions [slide]
The	Eniac Computer [slide]
Programming The	Eniac [slide]
Impact of	Enormous Miss Penalty [slide]
	Entropy [slide]
Meaning of	Entropy [slide]
Write Down	Equations [slide]
FSM	Equivalence [slide]
	Equivalent State Reduction [slide]
	Error Detection [slide]
Single-bit	Error Detection [slide]
	Error Correction [slide]
Hamming Distance and Bit	Errors [slide]
Detecting Multi-bit	Errors [slide]
Solution:	Escapement Strategy (2 Gates) [slide]
Bounded Buffer Problem with	Even More Semaphores [slide]
An	Evolutionary Step [slide]
	Exception Processing [slide]
	Exception Implementation [slide]
	Exception Handling Logic [slide]
	Exception + Interrupt Logic [slide]
	Exception Hardware [slide]
	Exception Handling [slide]
	Exceptions [slide]
	Exceptions I [slide]
	Exceptions II [slide]
	Exceptions [slide]
When Can	Exceptions Happen? [slide]
Resolving	Exceptions [slide]
Multiple	Exceptions? [slide]
Semaphores for Mutual	Exclusion [slide]
Pipelined	Execution Example [slide]
Example serial link: PCI	Express (PCIe) [slide]
UASM	Expressions and Layout [slide]
Compiling	Expressions [slide]
	Extending K-maps to 4-variable Tables [slide]
	Extending the Memory Hierarchy [slide]
	FETs Come in Two Flavors [slide]
	FIFO Buffering [slide]
	FSM States [slide]
	FSM Equivalence [slide]
Control	FSM for Factorial [slide]
Control	FSM Hardware [slide]
A Control	FSM for Factorial [slide]
New Problem → New Control	FSM [slide]
	FSM Limitations [slide]
	FSMs All the Way Down? [slide]
	Factorial with Pseudoinstructions [slide]
Putting It All Together:	Factorial [slide]
Example:	Factorial I [slide]
Example:	Factorial II [slide]
Datapath for	Factorial [slide]
Control FSM for	Factorial [slide]
A Control FSM for	Factorial [slide]
Can We Solve	Factorial with ALU Instructions? [slide]
Can We Solve	Factorial Now? [slide]
Putting It All Together:	Factorial [slide]
Why Did Our System	Fail? [slide]
So	Far: Single-purpose Hardware [slide]
	Faster ROMs [slide]
Wanted:	Faster Carry Logic! [slide]
Example: Page	Fault [slide]
Page	Faults [slide]
Approach: Incremental	Featurism [slide]
Memory: Using	Feedback [slide]
Instruction	Fetch/Decode [slide]
	Fewer Transitions → Lower Power [slide]
Example UASM Source	File [slide]
Multi-ported Register	File [slide]
Register	File Timing [slide]
5-stage Beta:	Final Version [slide]
	Finding Implicants [slide]
	Finding Prime Implicants [slide]
Abstraction du jour:	Finite State Machines [slide]
Procedure Linkage:	First Try [slide]
	Fix: “Snoopy” Cache Coherence Protocol [slide]
	Fixed-length Encodings [slide]
	Flakey Control Systems [slide]
Non-Volatile Storage:	Flash [slide]
FETs Come in Two	Flavors [slide]
Common IR: Control	Flow Graph [slide]
Control	Flow Graph for GCD [slide]
	Flow Control Problems [slide]
Interfaces Last	Forever [slide]
	Forget Circuits... Let’s solve a Real Problem [slide]
Things To Look	Forward To... [slide]
Stack	Frame Details [slide]
Stack	Frames as Activation Records [slide]
	From Atoms to Amazon [slide]
Where Does Noise Come	From? [slide]
	Frontend Stages: Lexical Analysis [slide]
	Frontend Stages: Syntactic Analysis [slide]
	Frontend Stages: Semantic Analysis [slide]
	Fully Bypassed Pipeline [slide]
	Fully-Associative Cache [slide]
	Fun With Stacks [slide]
The Universal	Function [slide]
	Functional Specifications [slide]
Communications	Futures [slide]
8-bit CLA (generate	G & P) [slide]
Control Flow Graph for	GCD [slide]
Turing Machines	Galore! [slide]
General CMOS	Gate Recipe [slide]
CMOS	Gates Are Naturally Inverting [slide]
Lenient	Gates [slide]
Solution: Escapement Strategy (2	Gates) [slide]
	Gates, Wires, & Delays [slide]
	General CMOS Gate Recipe [slide]
Code	Generation [slide]
Karnuagh Maps: A	Geometric Approach [slide]
Prime Implicants,	Glitches & Leniency [slide]
Common IR: Control Flow	Graph [slide]
Control Flow	Graph for GCD [slide]
The	HW/SW Balance [slide]
	Hamming Distance [slide]
	Hamming Distance and Bit Errors [slide]
Example: Match	Handler to OS [slide]
Which	Handler and OS? #1 [slide]
Which	Handler and OS? #2 [slide]
Which	Handler and OS? #3 [slide]
Example: Timer Interrupt	Handler [slide]
Interrupt	Handler Coding [slide]
Illop	Handler [slide]
	Handler for Actual Illops [slide]
	Handler for SVCs [slide]
New SVC	Handlers [slide]
Asynchronous I/O	Handling [slide]
Exception	Handling Logic [slide]
Beta Interrupt	Handling [slide]
Exception	Handling [slide]
When Can Exceptions	Happen? [slide]
Non-Volatile Storage:	Hard Disk [slide]
Now Put It in	Hardware [slide]
Control FSM	Hardware [slide]
So Far: Single-purpose	Hardware [slide]
	Hardware Support for Semaphores [slide]
Exception	Hardware [slide]
Reminder:	Hardware Caches [slide]
The Cache	Has Two Customers! [slide]
Pipeline	Hazards [slide]
Data	Hazards [slide]
Resolving	Hazards I [slide]
Resolving Data	Hazards I [slide]
Resolving Data	Hazards II [slide]
Summary: Pipelining with Data	Hazards [slide]
Control	Hazards I [slide]
Control	Hazards II [slide]
Resolving Control	Hazards [slide]
Resolving Control	Hazards With Stalls [slide]
Stall Logic For Control	Hazards [slide]
Resolving	Hazards II [slide]
Resolving	Hazards with Speculation I [slide]
Resolving	Hazards with Speculation II [slide]
Speculation Logic For Control	Hazards [slide]
Reminder: Resolving	Hazards [slide]
Compilers Can	Help [slide]
	Here’s a Design Approach [slide]
	Hexadecimal Notation [slide]
Memory	Hierarchy Interface [slide]
Memory	Hierarchy Interface [slide]
A Typical Memory	Hierarchy [slide]
Reminder: A Typical Memory	Hierarchy [slide]
Reminder: A Typical Memory	Hierarchy [slide]
Extending the Memory	Hierarchy [slide]
Example: How	High of a Hit Ratio? [slide]
	High-level Languages [slide]
Example: How High of a	Hit Ratio? [slide]
Um, About That	Hold Time... [slide]
	Housekeeping Issues... [slide]
	How Does It Get Assembled? [slide]
Example:	How High of a Hit Ratio? [slide]
	How Do 6.004 Students Do Laundry? [slide]
	How Can We Reduce Power? [slide]
	Huffman’s Algorithm [slide]
OS Organization:	I/O Devices [slide]
Asynchronous	I/O Handling [slide]
Interrupt-based Asynch	I/O [slide]
Instruction-level Parallelism	(ILP) [slide]
Intermediate Representation	(IR) [slide]
	IR Optimization [slide]
Example	IR Optimizations I [slide]
Example	IR Optimizations II [slide]
Example	IR Optimizations II [slide]
Example	IR Optimizations III [slide]
Example	IR Optimizations IV [slide]
Example	IR Optimizations IV [slide]
Common	IR: Control Flow Graph [slide]
Beta	ISA Summary [slide]
Reminder: Beta	ISA [slide]
Instruction Set Architecture	(ISA) [slide]
	ISA Design [slide]
Beta	ISA Summary [slide]
	ISA Issues: Simple vs. Complex Branches [slide]
Beta	ISA: Storage [slide]
Beta	ISA: Instructions [slide]
Mr. Blue Visits the	ISS [slide]
Mr. Blue Visits the	ISS (cont&rsquo'd.) [slide]
Example IR Optimizations	IV [slide]
Example IR Optimizations	IV [slide]
N-Channel MOSFET	$I_{DS}$ vs. $V_{DS}$ [slide]
Key	Idea: Stored-program Computer [slide]
But, What	If... [slide]
	Ill-formed Pipeline [slide]
	Illop Handler [slide]
Handler for Actual	Illops [slide]
	Impact of Enormous Miss Penalty [slide]
Exception	Implementation [slide]
CMOS Sum-of-products	Implementation [slide]
Systematic	Implementation Strategies [slide]
	Implementation Details [slide]
Strong Priority	Implementation [slide]
	Implementation Sketch #1 [slide]
	Implementation Sketch #2 [slide]
Pipelined	Implementation [slide]
Stack	Implementation [slide]
Semaphore	Implementation [slide]
Virtual Memory	Implementation: Paging [slide]
Vector Processing	Implementations [slide]
	Implementing Procedures [slide]
Finding	Implicants [slide]
Finding Prime	Implicants [slide]
Prime	Implicants, Glitches & Leniency [slide]
Associativity	Implies Choices [slide]
	Improving on the Bus [slide]
	Improving 5-Stage Pipeline Performance [slide]
	Improving 5-Stage Pipeline Performance [slide]
	Improving Speed: Adder Example [slide]
	Increase Throughput With Pipelining [slide]
Solution: Delay	Increases Reliability [slide]
Approach:	Incremental Featurism [slide]
Encoding	Information [slide]
Representing	Information with Voltage [slide]
	Information Processing = Computation [slide]
Quantifying	Information [slide]
	Information Conveyed by Data [slide]
Example:	Information Content [slide]
Probability and	Information Content [slide]
What is	Information? [slide]
ANDs and ORs with > 2	Inputs [slide]
Beta	Inside! [slide]
	Insight: We Need a Stack! [slide]
	Instruction Fetch/Decode [slide]
Load	Instruction I [slide]
Load	Instruction II [slide]
Store	Instruction I [slide]
Store	Instruction II [slide]
JMP	Instruction I [slide]
JMP	Instruction II [slide]
Load Relative	Instruction [slide]
LDR	Instruction I [slide]
LDR	Instruction II [slide]
	Instruction Set Architecture (ISA) [slide]
Beta JMP	Instruction [slide]
	Instruction-level Parallelism (ILP) [slide]
Emulated	Instruction: swapreg(Ra,Rc) [slide]
Assembly of	Instructions [slide]
UASM Macros for Beta	Instructions [slide]
ALU	Instructions [slide]
BEQ/BNE	Instructions I [slide]
BEQ/BNE	Instructions II [slide]
	Instructions [slide]
Beta ISA:	Instructions [slide]
Beta ALU	Instructions [slide]
Beta ALU	Instructions with Constant [slide]
Beta Load and Store	Instructions [slide]
Beta Branch	Instructions [slide]
Can We Solve Factorial with ALU	Instructions? [slide]
Encoding Postive	Integers [slide]
Encoding Signed	Integers [slide]
Buses,	Interconnect, So...? [slide]
Memory Hierarchy	Interface [slide]
Memory Hierarchy	Interface [slide]
	Interface Standard: Backplane Bus [slide]
	Interfaces Last Forever [slide]
System	Interfaces & Modularity [slide]
Circuit	Interleaving I [slide]
Circuit	Interleaving II [slide]
Circuit	Interleaving III [slide]
	Intermediate Representation (IR) [slide]
	Interpretation [slide]
	Interpretation vs. Compilation [slide]
	Interprocess Communication [slide]
	Interrupt Latency [slide]
Sources of	Interrupt Latency [slide]
	Interrupt Load [slide]
Exception +	Interrupt Logic [slide]
Beta	Interrupt Handling [slide]
Example: Timer	Interrupt Handler [slide]
	Interrupt Handler Coding [slide]
One	Interrupt at a Time [slide]
	Interrupt-based Asynch I/O [slide]
Recurring	Interrupts [slide]
Asynchronous	Interrupts [slide]
Key Technology: Timer	Interrupts [slide]
CMOS	Inverter VTC [slide]
Beyond	Inverters [slide]
CMOS Gates Are Naturally	Inverting [slide]
CMOS Loves	Inverting Logic [slide]
Why	Isn’t This a 20-minute Lecture? [slide]
One Last Timing	Issue [slide]
Housekeeping	Issues... [slide]
ISA	Issues: Simple vs. Complex Branches [slide]
compile_statement:	Iteration [slide]
	JMP Instruction I [slide]
	JMP Instruction II [slide]
Beta	JMP Instruction [slide]
Extending	K-maps to 4-variable Tables [slide]
	Karnuagh Maps: A Geometric Approach [slide]
	Key Idea: Stored-program Computer [slide]
Coded Algorithms:	Key to CS [slide]
	Key Technology: Timer Interrupts [slide]
Using	LD and ST [slide]
	LDR Instruction I [slide]
	LDR Instruction II [slide]
	Labels and Offsets [slide]
Assembly	Language [slide]
Summary: Assembly	Language [slide]
Programming	Languages [slide]
Programming	Languages [slide]
High-level	Languages [slide]
One	Last Timing Issue [slide]
Interfaces	Last Forever [slide]
New Device: D	Latch [slide]
Communication Technologies:	Latency [slide]
Interrupt	Latency [slide]
Sources of Interrupt	Latency [slide]
Doing N Loads of	Laundry [slide]
How Do 6.004 Students Do	Laundry? [slide]
Amdahl’s	Law [slide]
Amdahl’s	Law and Parallelism [slide]
UASM Expressions and	Layout [slide]
Why Isn’t This a 20-minute	Lecture? [slide]
Then a Little to the	Left... [slide]
A Plea for	Lenience [slide]
Prime Implicants, Glitches &	Leniency [slide]
	Lenient Gates [slide]
6.004: The Big	Lesson [slide]
	Lessons learned: single driver; point-to-point [slide]
	Lessons learned: clock recovery [slide]
	Let’s Build a System! [slide]
Forget Circuits...	Let’s solve a Real Problem [slide]
	Let’s Try it Out! [slide]
	Let's Build a RoboAnt [slide]
Frontend Stages:	Lexical Analysis [slide]
Digital State: What We'd	Like to Build [slide]
FSM	Limitations [slide]
	Limits to Pipeline Depth [slide]
	Limits to Single-Processor Performance [slide]
Bus	Lines as Transmission Lines [slide]
Bus Lines as Transmission	Lines [slide]
Solving Procedure	Linkage Problems [slide]
Procedure	Linkage Templates [slide]
Procedure	Linkage: First Try [slide]
Procedure	Linkage: The Contract [slide]
Combinational Device Wish	List [slide]
A	Little to the Right... [slide]
Then a	Little to the Left... [slide]
And Add A	Little Parallelism... [slide]
... With a	Little Discipline [slide]
	Load Instruction I [slide]
	Load Instruction II [slide]
	Load Relative Instruction [slide]
Interrupt	Load [slide]
Beta	Load and Store Instructions [slide]
One	Load At a Time [slide]
	Load-to-Use Stalls [slide]
Doing N	Loads of Laundry [slide]
Doing N	Loads... The 6.004 Way [slide]
The	Locality Principle [slide]
Accessing User	Locations [slide]
	Logarithmic-latency Networks [slide]
Control	Logic [slide]
CMOS Loves Inverting	Logic [slide]
	Logic Simplification [slide]
	Logic According to ROMs [slide]
Stall	Logic [slide]
Bypass	Logic [slide]
Stall	Logic For Control Hazards [slide]
Speculation	Logic For Control Hazards [slide]
Exception Handling	Logic [slide]
Exception + Interrupt	Logic [slide]
Reduce Area With Sequential	Logic [slide]
Wanted: Faster Carry	Logic! [slide]
Things To	Look Forward To... [slide]
Carry	Look-ahead Adders (CLA) [slide]
Translation	Look-aside Buffer (TLB) [slide]
Synthesis By Table	Lookup [slide]
	Lost in Space [slide]
CMOS	Loves Inverting Logic [slide]
Fewer Transitions →	Lower Power [slide]
Example:	MESI Cache Coherence Protocol [slide]
	MESI Activity Diagram [slide]
	MMU Address Translation [slide]
	MMU Address Translation [slide]
Putting it All Together:	MMU with TLB [slide]
N-Channel	MOSFET $I_{DS}$ vs. $V_{DS}$ [slide]
N-Channel	MOSFET: Physical View [slide]
N-Channel	MOSFET: Electrical View [slide]
We’ve Been Designing a	MUX [slide]
Our Memory	Machine [slide]
Our New	Machine [slide]
Building a Virtual	Machine (VM) [slide]
Abstraction du jour: Finite State	Machines [slide]
Turing	Machines [slide]
Turing	Machines Galore! [slide]
Mighty	Macroinstructions [slide]
UASM	Macros for Beta Instructions [slide]
Stack Management	Macros [slide]
Useful	Macros [slide]
Stack	Management Macros [slide]
Memory	Management & Protection [slide]
Simple Page	Map Design [slide]
Page	Map Arithmetic [slide]
Example: Page	Map Arithmetic [slide]
RAM-Resident Page	Maps [slide]
Multi-level Page	Maps [slide]
Karnuagh	Maps: A Geometric Approach [slide]
Noise	Margins [slide]
Example:	Match Handler to OS [slide]
	Meaning of Entropy [slide]
	Meanwhile, Outside the Box... [slide]
Performance	Measures [slide]
Our	Memory Machine [slide]
	Memory Technologies [slide]
Summary:	Memory Technologies [slide]
	Memory Hierarchy Interface [slide]
	Memory Hierarchy Interface [slide]
	Memory Reference Patterns [slide]
A Typical	Memory Hierarchy [slide]
Read-only	Memory (ROM) [slide]
Settable	Memory Element [slide]
Review: Virtual	Memory [slide]
Reminder: A Typical	Memory Hierarchy [slide]
Reminder: A Typical	Memory Hierarchy [slide]
Extending the	Memory Hierarchy [slide]
Virtual	Memory [slide]
Virtual	Memory Implementation: Paging [slide]
	Memory Management & Protection [slide]
Using Caches with Virtual	Memory [slide]
Summary: Virtual	Memory [slide]
	Memory: Using Capacitors [slide]
	Memory: Using Feedback [slide]
Virtual	Memory: the CS View [slide]
	Mesh Topologies [slide]
The Mysterious	Metastable State [slide]
	Metastable State: Properties [slide]
A Pipelining	Methodology [slide]
Cache	Metrics [slide]
	Mighty Macroinstructions [slide]
Boolean	Minimization [slide]
Impact of Enormous	Miss Penalty [slide]
Direct-Mapped Cache Problem: Conflict	Misses [slide]
Electrical	Model for Real Wires [slide]
The von Neumann	Model [slide]
	Model: Discrete Time [slide]
	Models of Computation [slide]
Other	Models of Computation [slide]
Other	Models of Computation [slide]
Anatomy of a	Modern Compiler [slide]
A	Modern Out-of-Order Superscalar Processor [slide]
System Interfaces &	Modularity [slide]
	More Building Blocks [slide]
	More Two’s Complement [slide]
Bounded Buffer Problem with	More Semaphores [slide]
Bounded Buffer Problem with Even	More Semaphores [slide]
	Mr. Blue Visits the ISS [slide]
	Mr. Blue Visits the ISS (cont&rsquo'd.) [slide]
Detecting	Multi-bit Errors [slide]
	Multi-level Page Maps [slide]
	Multi-ported Register File [slide]
	Multicore Processors [slide]
	Multicore Caches [slide]
Scheduling of	Multiple Devices [slide]
	Multiple Exceptions? [slide]
Processes:	Multiplexing the CPU [slide]
Binary	Multiplication [slide]
2's Complement	Multiplication [slide]
Combinational	Multiplier [slide]
2's Complement	Multiplier [slide]
Carry-save Pipelined	Multiplier [slide]
	Multiported SRAMs [slide]
Semaphores for	Mutual Exclusion [slide]
What’s	My Transition Diagram? [slide]
The	Mysterious Metastable State [slide]
Doing	N Loads of Laundry [slide]
Doing	N Loads... The 6.004 Way [slide]
	N-Channel MOSFET: Physical View [slide]
	N-Channel MOSFET: Electrical View [slide]
	N-Channel MOSFET $I_{DS}$ vs. $V_{DS}$ [slide]
	N-way Set-Associative Cache I [slide]
	N-way Set-Associative Cache II [slide]
Wide	NANDs and NORs [slide]
Wide NANDs and	NORs [slide]
CMOS Gates Are	Naturally Inverting [slide]
The	Need for “Real Time” [slide]
The	Need for Preemption [slide]
Insight: We	Need a Stack! [slide]
Procedure Storage	Needs [slide]
Logarithmic-latency	Networks [slide]
The von	Neumann Model [slide]
Anatomy of a von	Neumann Computer [slide]
Our	New Machine [slide]
	New Problem → New Control FSM [slide]
New Problem →	New Control FSM [slide]
	New Device: D Latch [slide]
Adding	New SVCs [slide]
	New SVC Handlers [slide]
Dealing With	Noise [slide]
Where Does	Noise Come From? [slide]
	Noise Margins [slide]
	Non-Volatile Storage: Flash [slide]
	Non-Volatile Storage: Hard Disk [slide]
The Case for a	Non-minimal SOP [slide]
Weak	(Non-preemptive) Priorities [slide]
Hexadecimal	Notation [slide]
	Now Put It in Hardware [slide]
Can We Solve Factorial	Now? [slide]
ANDs and	ORs with > 2 Inputs [slide]
	OS Organization: I/O Devices [slide]
Example: Match Handler to	OS [slide]
	OS Organization: Processes [slide]
Communicationg with the	OS [slide]
	OS Organization: Supervisor Calls [slide]
Which Handler and	OS? #1 [slide]
Which Handler and	OS? #2 [slide]
Which Handler and	OS? #3 [slide]
Labels and	Offsets [slide]
	Okay, Back to Circuits... [slide]
ALU	Op Datapath I [slide]
ALU	Op Datapath II [slide]
Should We Support Constant	Operands? [slide]
Best of Both Worlds: Overlapped	Operation [slide]
ALU	Operations (with constant) I [slide]
ALU	Operations (with constant) II [slide]
Data-Dependent Vector	Operations [slide]
IR	Optimization [slide]
	Optimization: keep values in regs [slide]
Example IR	Optimizations I [slide]
Example IR	Optimizations II [slide]
Example IR	Optimizations II [slide]
Example IR	Optimizations III [slide]
Example IR	Optimizations IV [slide]
Example IR	Optimizations IV [slide]
	Optimizing Your Design [slide]
Argument	Order & BP Usage [slide]
OS	Organization: I/O Devices [slide]
OS	Organization: Processes [slide]
OS	Organization: Supervisor Calls [slide]
	Other Models of Computation [slide]
	Other Models of Computation [slide]
Let’s Try it	Out! [slide]
A Modern	Out-of-Order Superscalar Processor [slide]
Uniprocessor	Outcome [slide]
What Are the Possible	Outcomes [slide]
Meanwhile,	Outside the Box... [slide]
Dealing With	Outside Corners [slide]
Thinking	Outside the Box [slide]
Best of Both Worlds:	Overlapped Operation [slide]
8-bit CLA (generate G &	P) [slide]
Example serial link:	PCI Express (PCIe) [slide]
Example serial link: PCI Express	(PCIe) [slide]
Simple	Page Map Design [slide]
	Page Faults [slide]
Example:	Page Fault [slide]
	Page Map Arithmetic [slide]
Example:	Page Map Arithmetic [slide]
RAM-Resident	Page Maps [slide]
Multi-level	Page Maps [slide]
Virtual Memory Implementation:	Paging [slide]
Demand	Paging [slide]
A	Parallel Bus Transaction [slide]
	Parallel Processing Summary [slide]
Instruction-level	Parallelism (ILP) [slide]
Data-Level	Parallelism [slide]
Amdahl’s Law and	Parallelism [slide]
Thread-Level	Parallelism [slide]
And Add A Little	Parallelism... [slide]
	Parity Check [slide]
Memory Reference	Patterns [slide]
Impact of Enormous Miss	Penalty [slide]
Processor	Performance [slide]
Processor	Performance [slide]
Improving 5-Stage Pipeline	Performance [slide]
Improving 5-Stage Pipeline	Performance [slide]
Limits to Single-Processor	Performance [slide]
Single-Cycle Beta	Performance [slide]
	Performance Measures [slide]
	Performance/Cost Analysis [slide]
Dining	Philosophers [slide]
N-Channel MOSFET:	Physical View [slide]
Example: Virtual →	Physical Translation [slide]
Using Voltages to Encode a	Picture [slide]
Improving 5-Stage	Pipeline Performance [slide]
Limits to	Pipeline Depth [slide]
Improving 5-Stage	Pipeline Performance [slide]
	Pipeline Hazards [slide]
	Pipeline Diagrams [slide]
Fully Bypassed	Pipeline [slide]
	Pipeline Diagrams [slide]
	Pipeline Conventions [slide]
Ill-formed	Pipeline [slide]
	Pipeline Example [slide]
5-Stage	Pipelined Processors [slide]
	Pipelined Implementation [slide]
5-Stage	Pipelined Datapath [slide]
	Pipelined Control [slide]
	Pipelined Execution Example [slide]
	Pipelined Cicuits [slide]
	Pipelined Components [slide]
Carry-save	Pipelined Multiplier [slide]
Wider or Superscalar	Pipelines [slide]
Summary:	Pipelining with Data Hazards [slide]
A	Pipelining Methodology [slide]
Increase Throughput With	Pipelining [slide]
A	Plea for Lenience [slide]
Serial,	Point-to-point Communications [slide]
Replacement	Policies [slide]
Write	Policy [slide]
A	Pop Quiz! [slide]
What Are the	Possible Outcomes [slide]
Encoding	Postive Integers [slide]
The	Power of Semaphores [slide]
CMOS Static	Power Dissipation [slide]
CMOS Dynamic	Power Dissipation I [slide]
CMOS Dynamic	Power Dissipation II [slide]
Fewer Transitions → Lower	Power [slide]
The	Power of Engineering Abstractions [slide]
How Can We Reduce	Power? [slide]
Semaphores for	Precedence [slide]
Registers are	Predefined Symbols [slide]
Branch	Prediction [slide]
The Need for	Preemption [slide]
Contexts: A Sneak	Preview [slide]
Finding	Prime Implicants [slide]
	Prime Implicants, Glitches & Leniency [slide]
The Locality	Principle [slide]
Weak (Non-preemptive)	Priorities [slide]
Setting	Priorities [slide]
Strong	Priority Implementation [slide]
	Probability and Information Content [slide]
New	Problem → New Control FSM [slide]
Forget Circuits... Let’s solve a Real	Problem [slide]
Example: Bounded Buffer	Problem [slide]
Bounded Buffer	Problem with Semaphores [slide]
Bounded Buffer	Problem with More Semaphores [slide]
Bounded Buffer	Problem with Even More Semaphores [slide]
Direct-Mapped Cache	Problem: Conflict Misses [slide]
Solving Procedure Linkage	Problems [slide]
Flow Control	Problems [slide]
Producer/Consumer Atomicity	Problems [slide]
	Procedure Calling Convention [slide]
	Procedure Linkage: First Try [slide]
	Procedure Storage Needs [slide]
Solving	Procedure Linkage Problems [slide]
	Procedure Linkage: The Contract [slide]
	Procedure Linkage Templates [slide]
Implementing	Procedures [slide]
	Procedures: A Software Abstraction [slide]
One VM For Each	Process [slide]
OS Organization:	Processes [slide]
	Processes: Multiplexing the CPU [slide]
Exception	Processing [slide]
Information	Processing = Computation [slide]
Vector	Processing Implementations [slide]
Parallel	Processing Summary [slide]
	Processor Performance [slide]
	Processor Performance [slide]
A Modern Out-of-Order Superscalar	Processor [slide]
5-Stage Pipelined	Processors [slide]
Multicore	Processors [slide]
	Producer/Consumer Atomicity Problems [slide]
A Simple	Programmable Datapath [slide]
	Programming Languages [slide]
	Programming Languages [slide]
	Programming The Eniac [slide]
	Propagation Delay [slide]
Metastable State:	Properties [slide]
Memory Management &	Protection [slide]
Fix: “Snoopy” Cache Coherence	Protocol [slide]
Example: MESI Cache Coherence	Protocol [slide]
	Pseudoinstructions [slide]
Factorial with	Pseudoinstructions [slide]
Now	Put It in Hardware [slide]
	Putting It All Together: Factorial [slide]
	Putting It All Together I [slide]
	Putting It All Together II [slide]
	Putting It All Together: Factorial [slide]
	Putting it All Together: MMU with TLB [slide]
	Quadratic-cost Topologies [slide]
	Quantifying Information [slide]
A Pop	Quiz! [slide]
Static	RAM (SRAM) [slide]
1T Dynamic	RAM (DRAM) Cell [slide]
	RAM-Resident Page Maps [slide]
Read-only Memory	(ROM) [slide]
	ROM Example [slide]
	ROM Example continued [slide]
Faster	ROMs [slide]
Logic According to	ROMs [slide]
	Rapid Context Switching [slide]
Example: How High of a Hit	Ratio? [slide]
	Raw Data [slide]
SRAM	Read [slide]
	Read-only Memory (ROM) [slide]
	ReadKey SVC: Attempt #1 [slide]
	ReadKey SVC: Attempt #2 [slide]
	ReadKey SVC: Attempt #3 [slide]
	ReadKey SVC: Attempt #4 [slide]
1T DRAM Writes and	Reads [slide]
Electrical Model for	Real Wires [slide]
Forget Circuits... Let’s solve a	Real Problem [slide]
	Real-world Consequences [slide]
CMOS	Recipe [slide]
General CMOS Gate	Recipe [slide]
Activation	Records [slide]
Stack Frames as Activation	Records [slide]
	Recurring Interrupts [slide]
	Recursion? [slide]
How Can We	Reduce Power? [slide]
	Reduce Area With Sequential Logic [slide]
Equivalent State	Reduction [slide]
Memory	Reference Patterns [slide]
Multi-ported	Register File [slide]
	Register File Timing [slide]
Edge-triggered D	Register [slide]
	Registers are Predefined Symbols [slide]
Summary of Dedicated	Registers [slide]
Load	Relative Instruction [slide]
Solution: Delay Increases	Reliability [slide]
	Reminder: Beta ISA [slide]
	Reminder: Single-Cycle Beta [slide]
	Reminder: Resolving Hazards [slide]
	Reminder: A Typical Memory Hierarchy [slide]
	Reminder: Hardware Caches [slide]
	Reminder: A Typical Memory Hierarchy [slide]
	Replacement Policies [slide]
Intermediate	Representation (IR) [slide]
	Representing Information with Voltage [slide]
Electricity to the	Rescue [slide]
	Resolving Hazards I [slide]
	Resolving Data Hazards I [slide]
	Resolving Data Hazards II [slide]
	Resolving Control Hazards [slide]
	Resolving Control Hazards With Stalls [slide]
	Resolving Hazards II [slide]
	Resolving Hazards with Speculation I [slide]
	Resolving Hazards with Speculation II [slide]
	Resolving Exceptions [slide]
Reminder:	Resolving Hazards [slide]
Semaphores for	Resource Allocation [slide]
	Returning to User-mode [slide]
	Review: Virtual Memory [slide]
A Little to the	Right... [slide]
Let's Build a	RoboAnt [slide]
The World Doesn’t	Run on Our Clock! [slide]
compile_expr(expr) →	Rx [slide]
The Case for a Non-minimal	SOP [slide]
Static RAM	(SRAM) [slide]
	SRAM Cell [slide]
	SRAM Read [slide]
	SRAM Write [slide]
Summary:	SRAM [slide]
Multiported	SRAMs [slide]
Using LD and	ST [slide]
New	SVC Handlers [slide]
ReadKey	SVC: Attempt #1 [slide]
ReadKey	SVC: Attempt #2 [slide]
ReadKey	SVC: Attempt #3 [slide]
ReadKey	SVC: Attempt #4 [slide]
Handler for	SVCs [slide]
Adding New	SVCs [slide]
Simple Timesharing	Scheduler [slide]
Sophisticated	Scheduling [slide]
	Scheduling of Multiple Devices [slide]
Ant	Schematic [slide]
Carry	Select Adders [slide]
32-bit Carry	Select Adder [slide]
	Self-timed Example [slide]
	Self-timed Example [slide]
Frontend Stages:	Semantic Analysis [slide]
	Semaphore Implementation [slide]
	Semaphores (Dijkstra) [slide]
	Semaphores for Precedence [slide]
	Semaphores for Resource Allocation [slide]
Bounded Buffer Problem with	Semaphores [slide]
Bounded Buffer Problem with More	Semaphores [slide]
	Semaphores for Mutual Exclusion [slide]
Bounded Buffer Problem with Even More	Semaphores [slide]
The Power of	Semaphores [slide]
	Semaphores as a Supervisor Call [slide]
Hardware Support for	Semaphores [slide]
A Simple	Sequential Circuit [slide]
	Sequential Consistency [slide]
Alternatives to	Sequential Consistency? [slide]
	Sequential Circuit Timing [slide]
Reduce Area With	Sequential Logic [slide]
	Serial, Point-to-point Communications [slide]
Instruction	Set Architecture (ISA) [slide]
N-way	Set-Associative Cache I [slide]
N-way	Set-Associative Cache II [slide]
	Settable Memory Element [slide]
	Setting Priorities [slide]
	Should We Support Constant Operands? [slide]
Synchronization: The Dark	Side [slide]
Encoding	Signed Integers [slide]
A	Simple Compilation Strategy [slide]
A	Simple Sequential Circuit [slide]
A	Simple Programmable Datapath [slide]
ISA Issues:	Simple vs. Complex Branches [slide]
	Simple Timesharing Scheduler [slide]
	Simple Page Map Design [slide]
Logic	Simplification [slide]
	Simplified Unpipelined Beta Datapath [slide]
	Simultaneous Transactions [slide]
Reminder:	Single-Cycle Beta [slide]
	Single-Cycle Beta Performance [slide]
Limits to	Single-Processor Performance [slide]
	Single-bit Error Detection [slide]
	Single-clock Synchronous Circuits [slide]
Timing in a	Single-clock System [slide]
So Far:	Single-purpose Hardware [slide]
Block	Size [slide]
Block	Size Trandeoffs [slide]
Implementation	Sketch #1 [slide]
Implementation	Sketch #2 [slide]
Branch Delay	Slots I [slide]
Branch Delay	Slots II [slide]
Contexts: A	Sneak Preview [slide]
	So Far: Single-purpose Hardware [slide]
Buses, Interconnect,	So...? [slide]
Procedures: A	Software Abstraction [slide]
One	Solution [slide]
	Solution: Delay Increases Reliability [slide]
	Solution: Escapement Strategy (2 Gates) [slide]
Can We	Solve Factorial with ALU Instructions? [slide]
Can We	Solve Factorial Now? [slide]
	Solving Procedure Linkage Problems [slide]
	Something We Can't Build (Yet) [slide]
	Sophisticated Scheduling [slide]
Example UASM	Source File [slide]
	Sources of Interrupt Latency [slide]
	Space & Time Constraints [slide]
Lost in	Space [slide]
CMOS Timing	Specifications [slide]
Functional	Specifications [slide]
Resolving Hazards with	Speculation I [slide]
Resolving Hazards with	Speculation II [slide]
	Speculation Logic For Control Hazards [slide]
Improving	Speed: Adder Example [slide]
	Stack Implementation [slide]
	Stack Management Macros [slide]
	Stack Frames as Activation Records [slide]
	Stack Frame Details [slide]
	Stack Detective [slide]
Insight: We Need a	Stack! [slide]
Fun With	Stacks [slide]
Frontend	Stages: Lexical Analysis [slide]
Frontend	Stages: Syntactic Analysis [slide]
Frontend	Stages: Semantic Analysis [slide]
	Stall Logic [slide]
	Stall Logic For Control Hazards [slide]
Load-to-Use	Stalls [slide]
Resolving Control Hazards With	Stalls [slide]
Interface	Standard: Backplane Bus [slide]
Abstraction du jour: Finite	State Machines [slide]
	State Transition Diagram [slide]
Valid	State Diagrams [slide]
	State Transition Diagram as a Truth Table [slide]
Discrete Time, Discrete	State [slide]
Equivalent	State Reduction [slide]
The Mysterious Metastable	State [slide]
Metastable	State: Properties [slide]
Digital	State: What We'd Like to Build [slide]
FSM	States [slide]
	Static RAM (SRAM) [slide]
CMOS	Static Power Dissipation [slide]
An Evolutionary	Step [slide]
Beta ISA:	Storage [slide]
	Storage Conventions [slide]
Procedure	Storage Needs [slide]
Non-Volatile	Storage: Flash [slide]
Non-Volatile	Storage: Hard Disk [slide]
	Store Instruction I [slide]
	Store Instruction II [slide]
Beta Load and	Store Instructions [slide]
Key Idea:	Stored-program Computer [slide]
	Straightforward Synthesis [slide]
Systematic Implementation	Strategies [slide]
A Simple Compilation	Strategy [slide]
Solution: Escapement	Strategy (2 Gates) [slide]
	Strong Priority Implementation [slide]
Control	Structure Alternatives [slide]
Control	Structure Taxonomy [slide]
How Do 6.004	Students Do Laundry? [slide]
	Sum-of-products Building Blocks [slide]
CMOS	Sum-of-products Implementation [slide]
Beta ISA	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary [slide]
Beta ISA	Summary [slide]
Parallel Processing	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary of Dedicated Registers [slide]
	Summary [slide]
	Summary [slide]
	Summary [slide]
	Summary: Assembly Language [slide]
	Summary: SRAM [slide]
	Summary: DRAM [slide]
	Summary: Memory Technologies [slide]
	Summary: Cache Tradeoffs [slide]
	Summary: Pipelining with Data Hazards [slide]
	Summary: Virtual Memory [slide]
Wider or	Superscalar Pipelines [slide]
A Modern Out-of-Order	Superscalar Processor [slide]
Semaphores as a	Supervisor Call [slide]
OS Organization:	Supervisor Calls [slide]
Should We	Support Constant Operands? [slide]
Hardware	Support for Semaphores [slide]
Rapid Context	Switching [slide]
Registers are Predefined	Symbols [slide]
	Synchronization: The Dark Side [slide]
The Bounded-tie	Synchronizer [slide]
Single-clock	Synchronous Circuits [slide]
	Synchronous Communication [slide]
Frontend Stages:	Syntactic Analysis [slide]
Straightforward	Synthesis [slide]
	Synthesis By Table Lookup [slide]
Computer	System Technologies [slide]
	System Interfaces & Modularity [slide]
Why Did Our	System Fail? [slide]
A Combinational Digital	System [slide]
Timing in a Single-clock	System [slide]
Let’s Build a	System! [slide]
	Systematic Implementation Strategies [slide]
Flakey Control	Systems [slide]
Translation Look-aside Buffer	(TLB) [slide]
Putting it All Together: MMU with	TLB [slide]
Synthesis By	Table Lookup [slide]
State Transition Diagram as a Truth	Table [slide]
Building the Transition	Table [slide]
Truth	Tables with Don’t Cares [slide]
Extending K-maps to 4-variable	Tables [slide]
Control Structure	Taxonomy [slide]
Combine	Techniques [slide]
Memory	Technologies [slide]
Summary: Memory	Technologies [slide]
Computer System	Technologies [slide]
Communication	Technologies: Latency [slide]
Key	Technology: Timer Interrupts [slide]
Procedure Linkage	Templates [slide]
Unsolvable?	That Can’t Be True... [slide]
Um, About	That Hold Time... [slide]
	Then a Little to the Left... [slide]
	Things To Look Forward To... [slide]
	Thinking Outside the Box [slide]
Is	This a Combination Device? [slide]
Why Isn’t	This a 20-minute Lecture? [slide]
	Thread-Level Parallelism [slide]
Increase	Throughput With Pipelining [slide]
The Need for “Real	Time” [slide]
Space &	Time Constraints [slide]
One Load At a	Time [slide]
Model: Discrete	Time [slide]
One Interrupt at a	Time [slide]
Discrete	Time, Discrete State [slide]
Um, About That Hold	Time... [slide]
Key Technology:	Timer Interrupts [slide]
Example:	Timer Interrupt Handler [slide]
Simple	Timesharing Scheduler [slide]
Register File	Timing [slide]
CMOS	Timing Specifications [slide]
One Last	Timing Issue [slide]
D-Register	Timing [slide]
	Timing in a Single-clock System [slide]
Sequential Circuit	Timing [slide]
Things To Look Forward	To... [slide]
Communications in	Today's Computers [slide]
Putting It All	Together I [slide]
Putting It All	Together II [slide]
Putting It All	Together: Factorial [slide]
Putting It All	Together: Factorial [slide]
Putting it All	Together: MMU with TLB [slide]
Communication	Topologies [slide]
Quadratic-cost	Topologies [slide]
Mesh	Topologies [slide]
CPU Design	Tradeoffs [slide]
Associativity	Tradeoffs [slide]
Summary: Cache	Tradeoffs [slide]
Block Size	Trandeoffs [slide]
A Parallel Bus	Transaction [slide]
Simultaneous	Transactions [slide]
Voltage	Transfer Characteristic [slide]
State	Transition Diagram [slide]
State	Transition Diagram as a Truth Table [slide]
What’s My	Transition Diagram? [slide]
Building the	Transition Table [slide]
Fewer	Transitions → Lower Power [slide]
MMU Address	Translation [slide]
Example: Virtual → Physical	Translation [slide]
	Translation Look-aside Buffer (TLB) [slide]
MMU Address	Translation [slide]
Bus Lines as	Transmission Lines [slide]
Encodings as Binary	Trees [slide]
Unsolvable? That Can’t Be	True... [slide]
	Truth Tables with Don’t Cares [slide]
State Transition Diagram as a	Truth Table [slide]
Let’s	Try it Out! [slide]
Procedure Linkage: First	Try [slide]
	Turing Machines [slide]
	Turing Machines Galore! [slide]
	Turing Universality [slide]
FETs Come in	Two Flavors [slide]
The Cache Has	Two Customers! [slide]
	Two’s Complement Encoding [slide]
More	Two’s Complement [slide]
A	Typical Memory Hierarchy [slide]
Reminder: A	Typical Memory Hierarchy [slide]
Reminder: A	Typical Memory Hierarchy [slide]
Example	UASM Source File [slide]
	UASM Macros for Beta Instructions [slide]
	UASM Expressions and Layout [slide]
	Um, About That Hold Time... [slide]
	Uncomputability! [slide]
Why f_H is	Uncomputable [slide]
	Uniprocessor Outcome [slide]
	Universal Building Blocks [slide]
The	Universal Function [slide]
	Universality [slide]
Turing	Universality [slide]
	Univsersality? [slide]
Simplified	Unpipelined Beta Datapath [slide]
	Unsolvable? That Can’t Be True... [slide]
Argument Order & BP	Usage [slide]
	Useful Macros [slide]
Accessing	User Locations [slide]
Returning to	User-mode [slide]
	Using Voltages to Encode a Picture [slide]
	Using Voltages Digitally [slide]
	Using LD and ST [slide]
Memory:	Using Capacitors [slide]
Memory:	Using Feedback [slide]
	Using Caches with Virtual Memory [slide]
Building a Virtual Machine	(VM) [slide]
One	VM For Each Process [slide]
CMOS Inverter	VTC [slide]
	VTC Deductions [slide]
	VTC Example [slide]
N-Channel MOSFET $I_{DS}$ vs.	$V_{DS}$ [slide]
	Valid State Diagrams [slide]
	Variable-length Encodings [slide]
Example:	Variable-length Encoding [slide]
	Vector Code Example [slide]
Data-Dependent	Vector Operations [slide]
	Vector Processing Implementations [slide]
5-stage Beta: Final	Version [slide]
N-Channel MOSFET: Physical	View [slide]
N-Channel MOSFET: Electrical	View [slide]
Virtual Memory: the CS	View [slide]
Review:	Virtual Memory [slide]
Building a	Virtual Machine (VM) [slide]
	Virtual Memory [slide]
	Virtual Memory Implementation: Paging [slide]
Example:	Virtual → Physical Translation [slide]
	Virtual Memory: the CS View [slide]
Using Caches with	Virtual Memory [slide]
Summary:	Virtual Memory [slide]
Mr. Blue	Visits the ISS [slide]
Mr. Blue	Visits the ISS (cont&rsquo'd.) [slide]
Representing Information with	Voltage [slide]
	Voltage Transfer Characteristic [slide]
Using	Voltages to Encode a Picture [slide]
Using	Voltages Digitally [slide]
	Wanted: Faster Carry Logic! [slide]
D-Register	Waveforms [slide]
FSMs All the	Way Down? [slide]
Doing N Loads... The 6.004	Way [slide]
	Weak (Non-preemptive) Priorities [slide]
	Where Does Noise Come From? [slide]
	Wide NANDs and NORs [slide]
	Wider or Superscalar Pipelines [slide]
Electrical Model for Real	Wires [slide]
Gates,	Wires, & Delays [slide]
Combinational Device	Wish List [slide]
The	World Doesn’t Run on Our Clock! [slide]
Best of Both	Worlds: Overlapped Operation [slide]
SRAM	Write [slide]
	Write Policy [slide]
	Write Down Equations [slide]
	Write-back [slide]
	Write-back with “Dirty” Bits [slide]
1T DRAM	Writes and Reads [slide]
Something We Can't Build	(Yet) [slide]
Optimizing	Your Design [slide]
8-bit CLA	(carry generation) [slide]
Lessons learned:	clock recovery [slide]
	compile_expr(expr) → Rx [slide]
	compile_statement [slide]
	compile_statement: Conditional [slide]
	compile_statement: Iteration [slide]
8-bit CLA	(complete) [slide]
ALU Operations (with	constant) I [slide]
ALU Operations (with	constant) II [slide]
Mr. Blue Visits the ISS	(cont&rsquo'd.) [slide]
ROM Example	continued [slide]
“Let me	count the ways.” [slide]
Lessons learned: single	driver; point-to-point [slide]
The Need for	“Real Time” [slide]
	“Let me count the ways.” [slide]
Why	f_H is Uncomputable [slide]
8-bit CLA	(generate G & P) [slide]
8-bit CLA (carry	generation) [slide]
Beta: Our	“Final Answer” [slide]
Write-back with	“Dirty” Bits [slide]
Optimization:	keep values in regs [slide]
Or take the	lazy route... [slide]
Lessons	learned: single driver; point-to-point [slide]
Lessons	learned: clock recovery [slide]
Example serial	link: PCI Express (PCIe) [slide]
“Let	me count the ways.” [slide]
Fix:	“Snoopy” Cache Coherence Protocol [slide]
Lessons learned: single driver;	point-to-point [slide]
Lessons learned: clock	recovery [slide]
Optimization: keep values in	regs [slide]
Or take the lazy	route... [slide]
Example	serial link: PCI Express (PCIe) [slide]
Lessons learned:	single driver; point-to-point [slide]
Forget Circuits... Let’s	solve a Real Problem [slide]
Emulated Instruction:	swapreg(Ra,Rc) [slide]
Or	take the lazy route... [slide]
Optimization: keep	values in regs [slide]
The	von Neumann Model [slide]
Anatomy of a	von Neumann Computer [slide]
“Let me count the	ways.” [slide]

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