### Standard Cell Library

The Standard Cell Library defines a set of logic gates, latches and registers to be used when doing gate-level simulation. These gates are simulated using Jade's built-in logic primitives, rather than as pullup and pulldown networks of FETs. The resulting increase in simulation speed makes it possible to simulate very large digital designs.

Each library element includes information about its timing specifications and size, used by the gate-level simulator to determine the performance and total size of your design. This information is based on a 180nm CMOS process, which is now out of date! Current state-of-the-art processes have sub-20nm features.

Module Function tCD (ns) tPD (ns) tR (ns/pf) tF (ns/pf) load (pf) size (μ2)
/gates/inverter $$z = \overline{a}$$ 0.005 0.02 2.30 1.20 0.007 10
/gates/buffer $$z = a$$ 0.020 0.08 2.20 1.20 0.003 13
/gates/buffer_h 0.020 0.07 1.10 0.60 0.005 17
/gates/tristate $$z = \left\{ \begin{array}{ll} a & e=1\\ \textrm{not driven} & e = 0 \end{array} \right.$$ 0.030 0.15 2.30 1.30 0.004 23
/gates/and2 $$z = a \cdot b$$ 0.030 0.12 4.50 2.30 0.002 13
/gates/and3 $$z = a \cdot b \cdot c$$ 0.030 0.15 4.50 2.60 0.002 17
/gates/and4 $$z = a \cdot b \cdot c \cdot d$$ 0.030 0.16 4.50 2.50 0.002 20
/gates/nand2 $$z = \overline{a \cdot b}$$ 0.010 0.03 4.50 2.80 0.004 10
/gates/nand3 $$z = \overline{a \cdot b \cdot c}$$ 0.010 0.05 4.20 3.00 0.005 13
/gates/nand4 $$z = \overline{a \cdot b \cdot c \cdot d}$$ 0.010 0.07 4.40 3.50 0.005 17
/gates/or2 $$z = a + b$$ 0.030 0.15 4.50 2.50 0.002 13
/gates/or3 $$z = a + b + c$$ 0.040 0.21 4.50 2.50 0.003 17
/gates/or4 $$z = a + b + c + d$$ 0.060 0.29 4.50 2.60 0.003 20
/gates/nor2 $$z = \overline{a + b}$$ 0.010 0.05 6.70 2.40 0.004 10
/gates/nor3 $$z = \overline{a + b + c}$$ 0.020 0.08 8.50 2.40 0.005 13
/gates/nor4 $$z = \overline{a+b+c+d}$$ 0.020 0.12 9.50 2.40 0.005 20
/gates/xor2 $$z = a \oplus b$$ 0.030 0.14 4.50 2.50 0.006 27
/gates/xnor2 $$z = \overline{a \oplus b}$$ 0.030 0.14 4.50 2.50 0.006 27
/gates/mux2 $$z = \left\{ \begin{array}{ll} d_0 & s=0\\ d_1 & s=1 \end{array} \right.$$ 0.020 0.12 4.50 2.50 0.005 27
/gates/mux4 $$z = \left\{ \begin{array}{ll} d_0 & s_1s_0=\textrm{0b00}\\ d_1 & s_1s_0=\textrm{0b01}\\ d_2 & s_1s_0=\textrm{0b10}\\ d_3 & s_1s_0=\textrm{0b11} \end{array} \right.$$ 0.040 0.19 4.50 2.50 0.006 66
/gates/dreg
tsetup=.15, thold=0
$$d \rightarrow q \textrm{ on } clk\uparrow$$ 0.030 0.19 4.30 2.50 0.002 56

Jade has a built-in memory device that can be used to model memories with a specified width and number of locations, and with one to three independent ports. Each port has 3 control signals and the specified number of address and data wires. You can instantiate a memory device in your circuit by clicking on MEM in the toolbar and dragging it onto the schematic. Then double-click the component to specify the width of the address (naddr, between 1 and 20), the width of the data (ndata, between 1 and 128), the number of ports, and (optionally) the initial contents. All the ports of a memory access the same internal storage, but each port operates independently.

Each port has the following connections:

OE is the output enable input for a read port. When 1, data is driven onto the data pins; when 0, the output pins are not driven by this memory port. If this port is only a write port, connect this terminal to ground (e.g., connect to the signal 0'1). If the port is only a read port and should always be enabled, connect this terminal to the power supply node (e.g., connect to the signal 1'1).

CLK is the clock input for write ports. When wen=1, data from the data terminals is written into the memory on the rising edge of clk. If this port is only a read port, connect this terminal to ground.

WE is the write enable input for write ports. See the description of CLK for details about the write operation. If this port is only a read port, connect this terminal to ground.

A[naddr-1:0] are the address inputs, listed most significant bit first. The values of these terminals are used to compute the address of the memory location to be read or written. The number of locations in the memory is determined by width of the address: nlocations = 2naddr.

D[ndata-1:0] are the data inputs/tristate outputs, listed most significant bit first.

The contents property can be used to specify the initial contents of a memory (if not specified, the memory is initialized to all X's). The memory is initialized, location-by-location, from the data values given in the list. The least significant bit (bit 0) of a value is used to initialize bit 0 of a memory location, bit 1 of a value is used to initialize bit 1 of a memory location, etc.

The contents property should be a list of numeric values separated by whitespace (spaces, tabs, newlines). You can use "0b" and "0x" notation to specify binary and hex values. The characters "+" and "_" are ignored and can be used to improve readability. The character "?" can be used in binary and hex values to represent "don't care" -- Jade will replace "?" with "0". Comments can be included in the contents using the standard "//" and "/* ... */" comment syntax.

Initialized memories are useful for modeling ROMs (e.g., for control logic) or simply for loading programs into the main memory of a processor. One caveat: if the memory has a write port and sees a rising clock edge with its write enable not equal to 0 and with one or more of the address bits undefined (i.e., with a value of "X"), the entire contents of the memory will also become undefined. So you should make sure that the write enable for a write port is set to 0 by your reset logic before the first clock edge, or else your initialization will be for naught.

The following options are the default values for the electrical and timing parameters for the memory.

tcd=seconds

the contamination delay in seconds. Default value = 20ps.

tpd=seconds

the propagation delay in seconds. This is how long it takes for changes in the address or output enable terminals to be reflected in the values driven by the data terminals. Default value is determined from the number of locations:

Number of locationstPDInferred type
nlocations ≤ 1282nsRegister file
128 < nlocations ≤ 10244nsStatic ram
nlocations > 102440nsDynamic ram

the output rise time in seconds per farad of output load. Default value is 1000, i.e., 1 ns/pf.

the output fall time in seconds per farad of output load. Default value is 500, i.e., 0.5 ns/pf.

input terminal capacitance in farads. Default value = 0.05pf.